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copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 98 db, 96 khz, multi-bit audio a/d converter features ! advanced multi-bit ? architecture ! 24-bit conversion ! supports audio sample rates up to 108 khz ! 98 db dynamic range at 5 v ! -90 db thd+n ! low-latency digital filter ! high-pass filter to remove dc offsets ! single +3.3 v or +5 v power supply ! power consumption less than 50 mw ! master or slave operation ! slave mode speed auto-detect ! master mode default settings ! 256x or 384x mclk/lrck ratio ! CS5343 supports i2s audio format ! cs5344 supports left-justified audio format general description the CS5343/4 is a complete analog-to-digital converter for digital audio systems. it performs sampling, analog- to-digital conversion, and ant i-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 108 khz per channel. the CS5343/4 uses a 3rd-order, multi-bit delta-sigma modulator followed by a digital filter, which removes the need for an external anti-alias filter. the CS5343/4 also features a high-impedance sam- pling network which elim inates costly external components such as op-amps. the CS5343/4 is available in a 10-pin tssop package for both commercial (-10 to +70 c) and automotive grades (-40 to +85 c). the cdb5343 customer dem- onstration board is also avai lable for device evaluation and implementation suggestions. please refer to the ?ordering information? on page 21 for complete details. the CS5343/4 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, dvd-karaoke players, dvd record- ers, a/v receivers, an d automotive applications. high-pass filter high-pass filter low-latency digital filters va 3.3 v to 5 v internal reference voltages high-z sampling network auto-detect mclk divider master clock single-ended analog input low-latency digital filters high-z sampling network single-ended analog input sclk lrck sdout filt+ vq ainr ainl serial port slave mode auto-detect high-pass filter august '06 ds687a4 CS5343/4
2 ds687a4 CS5343/4 table of contents 1. pin descriptions ........................................................................................................... ................... 4 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 5 specified operating conditions ... ................ ................. ................ ................ ................ ........... 5 absolute maximum rating s ................ ................. ................ ................ ............. ............. ........... ... 5 analog characteristics - commercial grade .................................................................... 6 analog characteristics - automotive grade ..................................................................... 7 digital filter characteristics ............................................................................................... .8 dc electrical characteristics ................................................................................................ 8 digital characteristics ....................................................................................................... ....... 9 system clocking and serial audio interface ................ ................ ............. ............. ......... 10 3. typical connection diagram ................................................................................................. .. 12 4. applications ............................................................................................................... .................... 13 4.1 operation as clock master or slave ........................................................................................ ....... 13 4.1.1 slave mode operation .................................................................................................... ....... 13 4.1.2 master mode operation ................................................................................................... ...... 14 4.1.2.1 master mode speed selection ............. ...................................................................... 14 4.1.3 master clock ............................................................................................................ ............. 14 4.2 serial audio interface .................................................................................................... ................. 15 4.3 digital interface ......................................................................................................... ...................... 15 4.4 analog connections ........................................................................................................ ............... 15 4.4.1 component values ........................................................................................................ ........ 16 4.5 grounding and power supply decoupling ..................................................................................... .16 4.6 synchronization of multiple devices ....................................................................................... ........ 17 5. filter plots ............................................................................................................. ...................... 17 6. parameter definitions ...................................................................................................... .......... 19 7. package dimensions ......................................................................................................... ........... 20 thermal characteristics ....................................................................................................... ... 20 8. ordering information ....................................................................................................... ......... 21 9. revision history ........................................................................................................... ................. 21 list of figures figure 1. CS5343 i2s serial audio interface .................................................................................... .......... 11 figure 2. cs5344 left-justified serial audio interface ......................................................................... ..... 11 figure 3. typical connection diagram........................................................................................... ............ 12 figure 4. i2s serial audio interface ........................................................................................... ................. 15 figure 5. left-justified serial audio interface ................................................................................ ............ 15 figure 6. CS5343/4 analog input network.............. .......................................................................... ......... 15 figure 7. CS5343/4 example analog input network................................................................................ .. 16 figure 8. single-speed mode stop band rejection ................................................................................. ... 17 figure 9. single-speed mode transition band .................................................................................... ...... 17 figure 10. single-speed mo de transition band (detail).......................................................................... .. 17 figure 11. single-speed mode passband ripple ................................................................................... ... 17 figure 12. double-speed mode stopband rejection................................................................................ .18 figure 13. double-speed mode tran sition band................................................................................... .... 18 figure 14. double-speed mode tran sition band (detail) .......................................................................... 18 figure 15. double-speed mode passband ripple................................................................................... .. 18
ds687a4 3 CS5343/4 list of tables table 1. master/slave mode sele ction ........................................................................................... ........... 13 table 2. speed modes and the associated sample ra tes (fs) in slave mode......................................... 13 table 3. speed modes and the associated sample rate s (fs) in master mode....................................... 14 table 4. speed mode selection in master mode .... ............................................................................... .... 14 table 5. common mclk frequencies in master and slave modes .......................................................... 14 table 6. analog input design pa rameters ........................................................................................ ......... 16
4 ds687a4 CS5343/4 1. pin descriptions pin name pin # pin description sdout 1 serial audio data output ( output ) - output for two?s complement serial audio data. also selects master or slave mode. sclk 2 serial clock ( input/output ) - serial clock for the serial audio interface. lrck 3 left right clock ( input/output ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 4 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. filt+ 5 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. ainl ainr 6 8 analog input ( input ) - the full-scale analog input level is specified in the analog characteristics specifi- cation table. vq 7 quiescent voltage (output) - filter connection for the internal quiescent reference voltage. gnd 9 ground ( input ) - ground reference. must be connected to analog ground. va 10 power ( input ) - positive power supply for the digital and analog sections. 1 2 3 4 5 6 7 8 9 10 sdout sclk lrck mclk filt+ va gnd ainr vq ainl
ds687a4 5 CS5343/4 2. characteristics and specifications (all min/max characteristics and spec ifications are guaranteed over the specified operating conditions . typical performance characteristics and specif ications are derived from measuremen ts taken at typical supply voltages and t a = 25 c.) specified operating conditions (gnd = 0 v, all voltages with respect to gnd.) absolute maximum ratings (gnd = 0 v, all voltages with respect to gnd.) (note 1) notes: 1. operation beyond these limits may result in permane nt damage to the device. normal operation is not guaranteed at these extremes. 2. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 3. the maximum over/under voltage is limited by the input current. parameter symbol min typ max unit power supplies va 3.1 4.75 3.3 5.0 3.5 5.25 v v ambient operating te mperature commercial automotive t ac t ad -10 -40 - - 70 85 c c parameter symbol min max unit dc power supplies va -0.3 +6.0 v input current (note 2) i in -10 + 10 ma input voltage (note 3) v in -0.7 va+0.7 v ambient operating temper ature (power applied) t a -50 +115 c storage temperature t stg -65 +150 c
6 ds687a4 CS5343/4 analog characteristics - commercial grade test conditions (unless otherwise spec ified): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz; source impedance less than or equal to 2.5 k ? . notes: 4. referred to the typical full-scale input voltage dynamic performance for commercial grade va = 3.3 v va = 5.0 v single-speed mode fs = 48 khz symbol min typ max min typ max unit dynamic range a-weighted unweighted 89 86 95 92 - - 92 89 98 95 - - db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db thd+n - - - -86 -75 -35 -80 - - - - - -90 -78 -38 -84 - - db db db double-speed mode fs = 96 khz min typ max min typ max unit dynamic range a-weighted unweighted 89 86 95 92 - - 92 89 98 95 - - db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db thd+n - - - -86 -75 -35 -80 - - - - - -90 -78 -38 -84 - - db db db dynamic performance for commercial grade - all modes min typ max unit interchannel isolation - 90 - db dc accuracy interchannel gain mismatch - - 0.1 db gain error -3 - +3 % gain drift - 100 - ppm/c analog input characteristics full-scale input voltage 0.51*va 0.56*va 0.57*va vpp input impedance - 7.5 - m ?
ds687a4 7 CS5343/4 analog characteristics - automotive grade test conditions (unless otherwise specif ied): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz; source impedance less than or equal to 2.5 k ? . notes: 5. referred to the typica l full-scale input voltage dynamic performance for automotive grade va = 3.3 v va = 5.0 v single-speed mode fs = 48 khz symbol min typ max min typ max unit dynamic range a-weighted unweighted 87 84 95 92 - - 90 87 98 95 - - db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db thd+n - - - -86 -75 -35 -78 - - - - - -90 -78 -38 -82 - - db db db double-speed mode fs = 96 khz min typ max min typ max unit dynamic range a-weighted unweighted 87 84 95 92 - - 90 87 98 95 - - db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db thd+n - - - -86 -75 -35 -78 - - - - - -90 -78 -38 -82 - - db db db dynamic performance for au tomotive grade - all modes min typ max unit interchannel isolation - 90 - db dc accuracy interchannel gain mismatch - - 0.1 db gain error -3 - +3 % gain drift - 100 - ppm/c analog input characteristics full-scale input voltage 0.51*va 0.56*va 0.57*va vpp input impedance - 7.5 - m ?
8 ds687a4 CS5343/4 digital filter characteristics notes: 6. response shown is for fs equal to 48 kh z. filter characteristics scale with fs. dc electrical characteristics (gnd = 0 v, all voltages with respect to 0 v. mclk=12.288 mhz; master mode) notes: 7. device enters power-down mode when mclk is held static. 8. valid with the recommended capacitor values on fi lt+ and vq as shown in the typical connection diagram. parameter symbol min typ max unit single-speed mode fs = 4 - 54 khz passband (-0.1 db) 0 - 0.489 fs passband ripple -0.025 - 0.025 db stopband 0.560 - - fs stopband attenuation 69 - - db total group delay (fs = output sample rate) t gd - 12/fs - s double-speed mode fs = 86 - 108 khz passband (-0.1 db) 0 - 0.489 fs passband ripple -0.025 - 0.025 db stopband 0.560 - - fs stopband attenuation 69 - - db total group delay (fs = output sample rate) t gd -9/fs- s high-pass filter characteristics frequency response -3.0 db -0.13 db (note 6) -1 20 - - hz hz phase deviation @ 20 hz (note 6) -10-deg passband ripple - - 0 db parameter symbol va = 3.3 v va = 5.0 v min typ max min typ max unit dc power supplies: va 3.1 3.3 - - 5 5.25 v power supply current (normal operation) i a -15-- 15 -ma power supply current (power-down mode) (note 7) i a -1.1- - 1.1 - ma power consumption (normal operation) (power-down mode) (note 7) - - - - 50 3.6 - - - - 75 5.5 - - mw mw parameter symbol min typ max unit power supply rejection ratio (1 khz) (note 8) psrr - 65 - db v q nominal voltage output impedance - - 0.44xva 25 - - v k ? filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - va 220 2.5 - - - v k ? ua
ds687a4 9 CS5343/4 digital characteristics parameter symbol min typ max units high-level input voltage (% of va) v ih 70 - - % low-level input voltage (% of va) v il --30% high-level output voltage at i o = 500 a(% of va) v oh 70 - - % low-level output voltage at i o =500 a(% of va) v ol --15% input leakage current i in -10 - 10 a
10 ds687a4 CS5343/4 system clocking and se rial audio interface (logic ?0? = gnd = 0 v; logic ?1? = va, c l = 20 pf) parameter symbol min typ max unit master mode mclk period (double-speed, 384x mode) t clkw 24 - 30 ns (double-speed, 192x mode) 48 - 60 ns (double-speed, 256x mode) 36 - 45 ns (double-speed, 128x mode) 72 - 90 ns (single-speed, 768x mode) 24 - 325 ns (single-speed, 384x mode) 48 - 651 ns (single-speed, 512x mode) 36 - 488 ns (single-speed, 256x mode) 72 - 976 ns mclk duty cycle 40 50 60 % output sample rate (single-speed) (double-speed) fs 4 86 - - 54 108 khz khz lrck duty cycle - 50 - % sclk duty cycle - 50 - % sdout valid before sclk rising t stp 10 - - ns sdout valid after sclk rising t hld 40 - - ns sclk falling to lrck edge t slrd -20 - 20 ns slave mode mclk period (double-speed, 384x mode) t clkw 24 - 30 ns (double-speed, 192x mode) 48 - 60 ns (double-speed, 256x mode) 36 - 45 ns (double-speed, 128x mode) 72 - 90 ns (single-speed, 768x mode) 24 - 325 ns (single-speed, 384x mode) 48 - 651 ns (single-speed, 512x mode) 36 - 488 ns (single-speed, 256x mode) 72 - 976 ns mclk duty cycle 40 50 60 % input sample rate (single-speed) (double-speed) fs 4 86 - - 54 108 khz khz lrck duty cycle 405060% sclk period t sclkw --ns sclk duty cycle 455055% sdout valid before sclk rising t stp 10 - - ns sdout valid after sclk rising t hld 10 - - ns sclk falling to lrck edge t slrd -20 - 20 ns 1 64 fs ------------------
ds687a4 11 CS5343/4 figure 1. CS5343 i2s serial audio interface tt stp hld msb msb-1 lrck sclk sdout t slrd t sclkw figure 2. cs5344 left-justified seri al audio interface tt stp hld msb msb-1 lrck sclk sdout t slrd t sclkw
12 ds687a4 CS5343/4 3. typical connection diagram figure 3. typical connection diagram ainl ainr 6 8 1 sdout 9 gnd 7 vq va 10 5 filt+ 2 sclk 3 lrck 4 mclk audio processor/ system clocks va or gnd va 3.3 v to 5 v CS5343/4 10 k ? 1 10 k ? 2 analog input conditioning 10 k ? 2 1 f 0.1 f 1 f 0.1 f 1 f 0.1 f see figure 6 on page 15 1 pull-up to va for master mode pull-down to gnd for slave mode 2 optional pull-up resistor for configur- ing clocks in master mode as desribed in the ?master mode speed selection? section on page 14
ds687a4 13 CS5343/4 4. applications 4.1 operation as cloc k master or slave the CS5343/4 supports operation as either a clock mast er or slave. as a clock master, the left/right and serial clocks are synchronously generated on-chip an d output on the lrck and sclk pins, respectively. as a clock slave, the lrck and sclk pins are always in puts and require external generation of the left/right and serial clocks. the selection of cl ock master or slave is made via a 10 k ? pull-up resistor from sdout to va for master mode selection or via a 10 k ? pull-down resistor from sdou t to gnd for slave mode se- lection, as shown in table 1 . 4.1.1 slave mode operation a unique feature of the CS5343/4 is the automatic sele ction of either single- or double-speed mode when acting as a clock slave. the auto-mode selection feat ure supports all standard audio sample rates from 4 to 108 khz. please refer to table 2 for supported sample rate ranges in slave mode. table 2. speed modes and the associated sample rates (fs) in slave mode mode selection master mode 10 k ? pull-up resistor from sdout to va slave mode 10 k ? pull-down resistor from sdout to gnd table 1. master/slave mode selection speed mode mclk/lrck ratio sclk/lrck ratio input sample rate range (khz) single-speed mode 256x 64 4 - 54 512x 64 4 - 54 384x 48, 64 4 - 54 768x 48, 64 4 - 54 double-speed mode 128x 64 86 - 108 256x 64 86 - 108 192x 48, 64 86 - 108 384x 48, 64 86 - 108
14 ds687a4 CS5343/4 4.1.2 master mode operation as clock master, the CS5343/4 generates lrck and sclk synchronously on-chip. table 3 shows the available sample rates and associated clock ratios in master mode. 4.1.2.1 master mode speed selection during power-up in master mode, the lrck and sclk pins are inputs to configure speed mode and the output clock ratio. the lrck pin is pulled low intern ally to select single-speed mode by default, but dou- ble-speed mode is accessed with a 10 k ? pull-up resistor from lrck to va as shown in table 4 . simi- larly, the sclk pin is internally pulled-low by default to select a 256x mclk/lrck ratio, but a mclk/lrck ratio of 348x is accessed with a 10 k ? pull-up resistor from sclk to va as shown in table 4 . following the power-up routine, the lrck and sclk pins become clock outputs. 4.1.3 master clock the CS5343/4 requires a master clock (mclk) which runs the internal sampling circuits and digital filters. there is also an internal mclk divider which is automatically activated based on the frequency of the mclk. table 4 lists some common audio output sample rates and the required mclk frequency. speed mode mclk/lrck ratio sclk/lrck ratio input sample rate range (khz) single-speed mode 256x 64 4 - 54 512x 64 4 - 54 384x 64 4 - 54 768x 64 4 - 54 double-speed mode 128x 64 86 - 108 256x 64 86 - 108 192x 64 86 - 108 384x 64 86 - 108 table 3. speed modes and the associated sample rates (fs) in master mode pin resistor option clock configuration lrck internal pull-dow n to gnd (100 k ? ) single-speed mode (default) external pull-up to va (10 k ? ) double-speed mode sclk internal pull-dow n to gnd (100 k ? ) 256x mclk/lrck (default) external pull-up to va (10 k ? ) 384x mclk/lrck table 4. speed mode selection in master mode master and slave mode sample rate (khz) speed mode mclk(mhz) mclk (mhz) 256x 512x 384x 768x 32 ssm 8.912 16.384 12.288 24.576 44.1 ssm 11.289 22.579 16.934 33.868 48 ssm 12.288 24.576 18.432 36.864 sample rate (khz) speed mode mclk(mhz) mclk (mhz) 128x 256x 192x 384x 88.2 dsm 11.289 22.579 16.934 33.868 96 dsm 12.288 24.576 18.432 36.864 table 5. common mclk frequencies in master and slave modes
ds687a4 15 CS5343/4 4.2 serial audio interface the CS5343 output is serial data in i2s audio format and the cs5344 output is serial data in left-justified audio format. figures 4 and 5 show the i2s and left-justified data re lative to sclk and lrck. additionally, figures 1 and 2 display more information on the required timing for the serial audio interface format. for an overview of serial audio interface formats, pl ease refer to cirrus application note an282. 4.3 digital interface va supplies power to both the analog and digital sections of the adc, and also po wers the serial port. con- sequently, the digital interface logic level must equal va to within the limits specified under ?digital charac- teristics? on page 9 . 4.4 analog connections the analog modulator samples the input signal at half of the internal master clock rate, or 6.144 mhz when mclk = 12.288 mhz. the digi tal filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are mu ltiples of the input sampling frequency (n 6.144 mhz), where n=0,1,2,... refer to figure 6 which shows the recommended topology of the analog input network. the ex- ternal shunt capacitor and internal input impedance fo rm a single-pole rc filter to provide the appropriate filtering of noise at the modulator sampling frequency . additionally, the 180 pf capacitor acts as a charge source for the internal sampling circ uits. capacitors of npo or other hi gh-quality dielectric will produce the best results while capacitors with a large voltage coe fficient (such as general-purpose ceramics) can de- grade signal linearity. figure 4. i2s serial audio interface sdata 23 22 8 7 23 22 sclk lrck 23 22 65 43 21 0 87 65 43 21 0 9 9 left channel right channel figure 5. left-justifie d serial audio interface sdata 23 22 7 6 23 22 sclk lrck 23 22 54 32 10 8 76 54 32 10 8 9 9 left channel right channel figure 6. CS5343/4 analog input network CS5343/4 ain input r1 r2 1 f 180pf c0g
16 ds687a4 CS5343/4 4.4.1 component values three parameters determine the values of resistors r1 and r2 as shown in figure 6 : source impedance, attenuation, and input impedance. table 6 shows the design equation used to determine these values. ? source impedance: source impedance is defined as the impedance as seen from the adc looking back into the signal network. the adc achieves optimal thd+n performance with a source imped- ance less than or equal to 2.5 k ? . ? attenuation: the required attenuation factor depends on the magnitude of the input signal. the full- scale input voltage is specified under ?analog characteristics - commercial grade? on page 6 . the user should select values for r1 and r2 such th at the magnitude of the incoming signal multiplied by the attenuation factor is less than or equal to the full-scale input voltage of the device. ? input impedance: input impedance is the impedance from t he signal source to the adc analog input pins. table 6 shows the input parameters and the associated design equations. figure 7 illustrates an example conf iguration using two 4.99 k ? resistors in place of r1 and r2. based on the discussion above, this circuit provides an optim al interface for both the adc and the signal source. first, consumer equipment frequently requires an input impedance of 10 k ?, which the 4.99 k ? resistors provide. second, this circuit will atte nuate a typical line level voltage, 2 vrms, to the full-scale input of the adc, 1 vrms when va = 5 v. finally, at 2.5 k ?, the source impedance optimizes analog performance of the adc. 4.5 grounding and power supply decoupling as with any high-resolution converter, designing with t he CS5343/4 requires careful attention to power sup- ply and grounding arrangements if its potential performance is to be realized. figure 3 shows the recom- mended power arrangements, with va connected to a clean supply. decoupling capacitors should be as near to the adc as possible, with th e low value ceramic capacitor being the nearest. all signals, especially clocks, should be kept away from the filt+ and vq pi ns in order to avoid unwanted coupling into the mod- ulators. the filt+ and vq decoupling capacitors, part icularly the 0.01 f, must be positioned to minimize the electrical path from filt+ to gnd. the cdb534 3 evaluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the adc digital outputs only to cmos inputs. source impedance attenuation factor input impedance table 6. analog input design parameters r 1 r 2 () r 1 r 2 + ------------------------ - r 2 () r 1 r 2 + () ------------------------ - r 1 r 2 + () figure 7. CS5343/4 example analog input network CS5343/4 ain input 4.99 k ? 4.99 k ? 1 f 180pf c0g
ds687a4 17 CS5343/4 4.6 synchronization of multiple devices in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the mclk, sclk, and lrck must be the same for all of the CS5343 and cs5344 devices in the system. 5. filter plots figure 8. single-speed mode stopband rejection figure 9. single-speed mode transition band -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 .0 0 .1 0 .2 0.3 0.4 0.5 0.6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 10. single-speed mode transition band (d etail) figure 11. single-speed mode passband ripple -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db)
18 ds687a4 CS5343/4 figure 12. double-speed mode stopband rejectio n figure 13. double-speed mode transition band -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 14. double-speed mode transition band (d etail) figure 15. double-speed mode passband ripple
ds687a4 19 CS5343/4 6. parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the spec ified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement technique has been accept ed by the audio engineer ing society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter's output with no signal to the input under test and a full-sc ale signal applied to the ot her channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale an alog input for a full-scale digital output. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
20 ds687a4 CS5343/4 7. package dimensions notes: 1. reference document: jedec mo-187 2. d does not include mold flash or protru sions which is 0.15 mm max. per side. 3. e1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. exceptions to jedec dimension. thermal characteristics inches millimeters note dim min nom max min nom max a -- -- 0.0433 -- -- 1.10 a1 0 -- 0.0059 0 -- 0.15 a2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4 , 5 c 0.0031 -- 0.0091 0.08 -- 0.23 d -- 0.1181 bsc -- -- 3.00 bsc -- 2 e -- 0.1929 bsc -- -- 4.90 bsc -- e1 -- 0.1181 bsc -- -- 3.00 bsc -- 3 e -- 0.0197 bsc -- -- 0.50 bsc -- l 0.0157 0.0236 0.0315 0.40 0.60 0.80 l1 -- 0.0374 ref -- -- 0.95 ref -- 0--80--8 controlling dimension is millimeters parameter symbol min typ max unit allowable junction temperature t j --135 c junction to ambient thermal impedance (4-layer pcb) (2-layer pcb) ja-4 ja-2 - - 100 170 - - c/w c/w 10ld tssop (3 mm bo dy) package drawing (note 1) e n 1 23 e b a1 a2 a d seating plane e1 1 l side view end view top view l1 c
ds687a4 21 CS5343/4 8. ordering information 9. revision history product description package pb-free grade temp range container order # CS5343 98 db, multi-bit audio a/d converter, i2s audio format 10-tssop yes commercial -10 to +70 c rail CS5343-czz tape & reel CS5343-czzr CS5343 98 db, multi-bit audio a/d converter, i2s audio format 10-tssop yes automotive -40 to +85 c rail CS5343-dzz tape & reel CS5343-dzzr cs5344 98 db, multi-bit audio a/d converter, left-justified audio format 10-tssop yes commercial -10 to +70 c rail cs5344-czz tape & reel cs5344-czzr cs5344 98 db, multi-bit audio a/d converter, left-justified audio format 10-tssop yes automotive -40 to +85 c rail cs5344-dzz tape & reel cs5344-dzzr cdb5343 CS5343 evaluation board - no - - - cdb5343 release changes a2 changes made to serial port diagrams. see figure 1 and figure 2 on page 11 . a3 replaced block diagram on cover page. increased minimum hold time (thld) specification on page 10 . updated table 4, ?speed mode selection in master mode,? on page 14 . a4 corrected mclk timing specifications on page 10 corrected ?typical connection diagram? on page 12 corrected table 3, ?speed modes and the associated sample rates (fs) in master mode,? on page 14 contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (?critical applications?). cirr us products are not designed, au thorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer?s ri sk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchan tability and fitness for par ticular purpose, with rega rd to any cirrus product that is used in such a manner. if the customer or customer?s cu stomer uses or permits the use of cirrus products in critical applications, customer agrees, by such u se, to fully indemnify cirrus, its officers , directors, employees, distributors and other agents from any and all liability, including attorneys? fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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